1. Field of the Invention
The present invention relates to digital signal buffer circuits, and in particular, to digital signal buffer circuits employing complementary metal oxide semiconductor field effect transistors ("MOSFETs") for minimizing power consumption.
2. Description of the Related Art
Digital signal buffer circuits are commonly used for such purposes as signal or circuit isolation, impedance matching, or improvement of fan-in and fan-out characteristics. A common type of buffer circuit design is an inverter. A conventional inverter design 10 using complementary MOSFETs is shown in FIG. 1. The P-type MOSFET ("P-MOSFET") 12 and N-type MOSFET ("N-MOSFET") 14 are mutually coupled in a totem-pole configuration in which their gates 12g, 14g and drains 12d, 14d are connected to receive the input signal 16 to be buffered and provide the complementary output buffered signal 18, respectively.
The source 12s of the P-MOSFET 12 is connected to a positive voltage supply VDD and the source 14s of the N-MOSFET 14 is connected to a negative voltage supply VSS. Alternatively, if dual power supplies are not to be used, and instead a single positive power supply is to be used, the source 12s of the P-MOSFET 12 is connected to a positive voltage supply VCC and the source 14s of the N-MOSFET 14 is connected to the circuit reference, or ground GND.
The buffer circuit 10 of FIG. 1 consumes relatively low power due to its use of complementary MOSFETs 12, 14. However, its power consumption becomes more significant when it is used for buffering a transistor-transistor logic ("TTL") type of input signal 16 (with a VCC-GND power supply configuration). A TTL "0", or logical low, is very close to zero volts, but a TTL "1", or logical high, is generally far below the value of the positive supply voltage VCC. While VCC is typically equal to 5 volts, a TTL "1" is typically between 2 and 2.5 volts. Thus, although the application of a TTL "0" as the input signal 16 will generally turn the N-MOSFET 14 virtually completely off and the P-MOSFET 12 virtually completely on, a typical TTL "1" will not reliably turn the N-MOSFET 14 completely on or the P-MOSFET 12 completely off. Accordingly, when the input signal 16 is a TTL "1", the output signal 18 will be a TTL "0"; however, the buffer circuit 10 will still be dissipatinq DC power since the P-MOSFET 12 will not be completely turned off, and will therefore be conducting current to the N-MOSFET 14 which has been turned on.
Referring below to Tables 1A and 1B, typical supply (drain) currents for the MOSFETs 12, 14 (with channel widths and lengths as indicated) for the conventional buffer circuit 10 are shown for various VCC voltages and ambient temperatures. (Table 1A also includes representative worst case propagation delays for a full IC simulation including additional circuitry external to the buffer circuit 10.) It can be seen that a significant amount of supply current flows with the input signal 16 voltage equal to a typical TTL "1" level of two volts. Reductions in supply current are possible by properly scaling down the channels of the MOSFETs 12, 14, but at a cost of increased propagation delay.
TABLE 1A ______________________________________ CONVENTIONAL BUFFER CIRCUIT ______________________________________ MOSFET Type Channel Width Channel Length ______________________________________ P 43 microns 3.0 microns N 150 microns 2.6 microns ______________________________________ VCC = 4.75 volts dc; Temperature = 55.degree. C. Input (volts) Current (micro-amperes) ______________________________________ 2 1406.0 3 422.9 ______________________________________ Input Output Delay (nanoseconds) ______________________________________ L.sub.I .fwdarw.H.sub.I H.sub.O .fwdarw.L.sub.O 7.02 H.sub.I = 3 volts where: H.sub.I .fwdarw.L.sub.I L.sub.O .fwdarw.H.sub.O 6.80 L.sub.I = 0 volts ______________________________________
TABLE 1B ______________________________________ CONVENTIONAL BUFFER CIRCUIT ______________________________________ MOSFET Type Channel Width Channel Length ______________________________________ P 43 microns 3.0 microns N 150 microns 2.6 microns ______________________________________ VCC = 5.25 volts dc; Temperature = 27.degree. C. Input (volts) Current (micro-amperes) ______________________________________ 2 2163.0 3 899.1 ______________________________________ VCC = 5.25 volts dc; Temperature = 0.degree. C. Input (volts) Current (micro-amperes) ______________________________________ 2 2292.0 3 922.3 ______________________________________
Referring below to Table 2, it can be seen that with the channel widths for the P-MOSFET 12 and N-MOSFET 14 reduced to 8 and 28 microns, respectively, and the input signal 16 voltage at two volts, the total MOSFET drain current can be substantially reduced. However, it can been seen by comparing Tables 1 and 2 that the propagation delay also increases substantially. Thus, while scaling down the MOSFET geometries can substantially reduce the total drain current, a concomitant penalty is paid with respect to propagation delay.
TABLE 2 ______________________________________ CONVENTIONAL "LOW POWER" BUFFER CIRCUIT ______________________________________ MOSFET Type Channel Width Channel Length ______________________________________ P 8 microns 3.0 microns N 28 microns 2.6 microns ______________________________________ VCC = 4.75 volts dc; Temperature = 55.degree. C. Input (volts) Current (micro-amperes) ______________________________________ 2 268.50 3 80.16 ______________________________________ Input Output Delay (nanoseconds) ______________________________________ L.sub.I .fwdarw.H.sub.I H.sub.O .fwdarw.L.sub.O 7.63 H.sub.I = 3 volts where: H.sub.I .fwdarw.L.sub.I L.sub.O .fwdarw.H.sub.O 8.15 L.sub.I = 0 volts ______________________________________